1. Field of the Invention
The present invention relates, in general, to a semiconductor memory device and a method for fabrication thereof and, more particularly, to an improvement in securing capacitance and reliability, along with the method.
2. Description of the Prior Art
Important factors associated with the integration of a DRAM, a universal semiconductor memory device, are the reduction in cell area and charge storage capacitance. That is to say, the high integration of a semiconductor integrated circuit is accomplished with a great diminution of the unit area of chips and cells yet with securing sufficient charge storage capacitance. Accordingly, highly precise process techniques have been required for the sufficiency of charge storage capacitance of a cell as well as for the reliability of a cell.
In order to better understand the background of the present invention, a conventional semiconductor memory device will be generally described, along with its fabrication process, in connection with FIG. 1.
As shown in FIG. 1, the conventional semiconductor memory device is comprised broadly of a MOSFET and a capacitor. For the MOSFET, a semiconductor substrate 1 is first provided with a field oxide layer 2, and a gate oxide layer 3 is grown thereon. Subsequently, polysilicon is deposited for implantation of dopants and a pattern of a gate electrode 4 and a word line 4' is formed. And then, an oxide spacer 5 at a side wall of the gate electrode 4 is used to form active regions 6, 6' of lightly doped drain (LDD) structure, whereby the electrical properties of the MOSFET can be improved. For the capacitor, a blanket insulation oxide layer 7 is first formed over the MOSFET structure to planarize it, and then selectively etched to form a contact hole which exposes the active region 6 therethrough. Thereafter, impurity-doped polysilicon is deposited such that it comes into contact with the active region 6, and then patterned to form a storage electrode 11. On the storage electrode is grown a nitride-oxide (hereinafter referred to as "NO") or oxide-nitride-oxide (hereinafter referred to as "ONO") composite dielectric layer, on which impurity-doped polysilicon is deposited and then patterned for a plate electrode 16.
Now, such conventional semiconductor memory device has proved to be unsuitable for the high integration of a semiconductor device because it is virtually impossible with this structure for a storage electrode to secure sufficient capacitance and maintain the high integration.